With the increase of integration level of integrate circuits (ICs), the critical dimension (CD) of semiconductor devices has become smaller and smaller. When the CD of the semiconductor devices is continuously shrank, leak voltages of the semiconductor devices may be unable to be correspondingly decreased, thus electric fields of the channel regions between source regions and drain regions of the semiconductor devices may be significantly strong. Electrons of in semiconductor devices may be accelerated by secondary collisions to a speed that is multiple-times higher than a speed of thermal movement. The electrons with such a high speed may be referred as hot electrons. The hot electrons may cause a hot electron effect. The hot electron effect may cause the hot electrons to flow into gate dielectric layers of the semiconductor devices; and to form gate currents and substrate currents. Thus, the stability of the semiconductor devices and circuits may be affected.
In order to prevent the hot electron effect, a plurality of structures have been developed to improve structures of MOS transistors, such as dual infusion structures, embedded channel structures, discrete gate structures, lightly doped drain (LDD) structures or embedded drain structures, etc. Among of these structures, the LDD structures have attracted more research attentions, and have presented applicable possibilities. The LDD structures may reduce the electrical fields; and may significantly improve the hot electron effect.
Besides enhancing the performance of the MOS transistors by improving the hot electron effect, enhancing the performance of MOS transistors using stress has become a more and more common method because the stress may alter the band gap and carrier mobility of silicon. Carriers of NMOS transistor are electrons; and carriers of the PMOS transistors are holes. Specifically, by properly controlling the stress in channel regions of MOS transistor, the carrier mobility may be increased, so as to increase the drive current. Thus, the performance of the MOS transistors may be significantly enhanced.
For example, an embedded SiGe technology may be used to generate a compressive stress in the channel region of a PMOS transistor, the carrier mobility of the PMOS transistor may be increased. The embedded SiGe technology may refer to embedding SiGe in regions corresponding to a subsequently formed source region and a subsequently formed drain region in the semiconductor substrate. The embed SiGe may generate compressive stress to the channel region of the PMOS transistor because of the lattice mismatch between silicon and SiGe.
Theoretically, the embedded SiGe technology may increase the carrier mobility of transistors to a certain extent. However, in practical fabrication processes of the PMOS transistors, the carrier mobility of PMOS transistor may be still relatively low. Further, other devices and/or structures may be formed on a same substrate with the PMOS transistor, and a plurality of processes may be needed to etch and/or clean the substrate with the PMOS transistor, the devices and/or structures, thus the embedded SiGe may be damaged by the processes. The disclosed methods and devices are directed to solve one or more problems set forth above and other problems.